1. Field
Embodiments of the present invention relate to interconnect structures and fabrication methods. In particular, the embodiments relate to novel interconnect structures containing conductive electrolessly deposited etch stop layers and in some instances liner layers and via plugs, to novel methods for making the interconnect structures, and to integrated circuits containing the interconnect structures.
2. Background
Many integrated circuits contain multi-layer electrical interconnect structures to provide electrical signals to logic elements such as transistors located on a semiconductor substrate. The interconnect structures often contain interconnect lines which are spaced apart in a nearly coplanar arrangement within a dielectric material that insulates the lines from one another. Select connections between interconnect lines on different levels are made by vias formed through the insulating material.
The interconnect lines are often made of highly conductive metals or alloys. Copper has become a widely used material due in part to its low electrical resistance compared to other metals. However, one of the disadvantages of copper is that it readily oxidizes. Accordingly, if a copper surface is left exposed for prolonged periods of time, or subjected to a variety of etching or plasma cleaning operations, the surface may become oxidized. Unlike with other materials, such as aluminum, copper oxidation does not lead to a thin protective coating that blocks further oxidation, and significant portions of the copper may become oxidized. This is generally undesirable, since it may significant change the electrical and mechanical properties of the interconnect structure. Another disadvantage of copper is that it is easily etched with many of the commonly-used dielectric etching chemistries. Accordingly, if the copper surface is left exposed, and unprotected, it can become oxidized or partly removed during subsequent processing operations.
In order to reduce oxidation and copper etching, protective dielectric etch stop or hard mask layers are often formed on copper interconnect lines. Materials that are commonly used for this purpose include silicon nitride (SiN), silicon carbide (SiC), and silicon dioxide (SiO)2). Although these dielectric layers may be effective at protecting the copper from reaction, they often contribute to mechanical separations that lead to integrated circuit failure and they may increase the effective dielectric constant of the interconnect structure and lead to reduced performance.
The protective dielectric layers provide an additional material interface or junction where mechanical separation from the protective layers in the form of pilling, cracking, or blistering often occurs. These types of mechanical failures may reduce production yields and may decrease the effective lifetime of manufactured integrated circuits. This problem may be compounded when low dielectric constant materials (low-k), which have a dielectric constant less than silicon dioxide, are used for the interconnect structure, since these materials are often chemically different from the protective dielectric layer materials.
The protective dielectric materials may also increase the effective dielectric constant of the interconnect structure, particularly when the structure contains low-k dielectric materials. Such increases in the dielectric constant may effectively decrease the speed of the integrated circuit, which depends upon interconnect signal propagation speeds. This can lead to reduced performance of the integrated circuit.